1. Field of the Invention
The present invention relates to a semiconductor memory device and, more specifically, it relates to a semiconductor memory device which is capable of simultaneously carrying out function test of a plurality of memory cells at the time of testing whether the memory cells included in the semiconductor memory device properly function or not.
2. Description of the Prior Art
Recently, as a capacity of a semiconductor memory device comes to be larger and larger, the time required for testing whether the memory cells function properly or not becomes longer and longer. In order to solve this problem, a novel semiconductor memory device has been proposed which is capable of reducing much time required for the function test, in which, instead of the conventional function test carried out by successively reading the stored contents of the memory cells bit by bit, function tests of a plurality of memory cells are carried out simultaneously, by outputting a certain logic value outside the device when the information logic value simultaneously read from memory cells of a plurality of bits are the same (the operation mode in which the function tests of a plurality of memory cells are carried out simultaneously will be hereinafter referred to as test mode).
The semiconductor memory device provided with the test mode in which the function test of a plurality of memory cells are carried out simultaneously is disclosed in the U.S. Pat. No. 4,692 901 entitled "Semiconductor Memory" invented by M. Kumanoya et al. filed by the same applicant and issued on Sept. 8, 1987. The outline of the device disclosed in the above mentioned U.S. Patent is also disclosed in "A 90ns 1Mb DRAM with Multi-Bit Test Mode", M. Kumanoya et al, 1985 IEEE ISSCC Digest of Technical Papers, 1985, pp. 240-241, "A Reliable 1-Mbit DRAM with a Multi-Bit-Test Mode", M. Kumanoya et al, IEEE Journal of Solid-State Circuits. vol. Sc-20, No. 5, October 1985, pp. 909-912.
The above described articles are incorporated herein by reference as a prior or art.
FIG. 1 is a block diagram mainly showing the electrical structure of the output (reading) circuit portion of a conventional semiconductor memory device capable of test mode operation, disclosed in the above mentioned prior art.
The semiconductor device shown in FIG. 1 comprises a memory cell array 1 constituted by a plurality of memory cells arranged in two dimensions of rows and columns each storing logic value information, preamplifiers 2, 3, 4 and 5 respectively receiving the stored content of the memory cell selected from the memory cell array 1 by a selection means, not shown, and generating the stored content R1, R2, R3 and R4 of the memory cell and the inverted signals R1, R2, R3 and R4 thereof, transfer gate transistors 6 to 13 which turn on/off in response to a signal obtained from subdecoding, for example, the most significant address (row and column) out of external address signals and selectively pass the signals from the preamplifiers 2 to 5, an AND gate 21 which receives the signal information R1 to R4 from the premaplifiers 2 to 5 and outputs the logical product thereof, an AND gate 20 which receives the inverted signals R1 to R4 from the preamplifiers 2 to 5 and outputs the logical product thereof, normal mode/test mode selecting switch 22 which selectively passes, in response to the test mode designating signal TM applied from a control signal input terminal 23, any signal R, which is one of the output signals of the preamplifiers 2 to 5 (hereinafter referred to as internal output signals) R1 to R4, R, which is one of the internal signals R1 to R4, and either one of the AND gate 20 output R' or AND gate output R', a main amplifier 18 which receives the signal applied from the selecting switch 22 and amplifiers and outputs the same, output transistors 25 and 26 which turn on/off in response to the signal from the main amplifier 18, and external output terminal 19 for externally applying the signal applied from the node of the output transistors 25 and 26.
Although not shown, memory cell array is divided into four blocks. One memory cell from each block, namely, four memory cells in all are selected simultaneously based on external address signals, and respective stored contents are applied to the corresponding preamplifiers 2 to 5. The signals R1 to R4 read from the selected memory cells are amplified and invertedly amplified in the preamplifiers 2 to 5. Therefore, sets of signals complementary to each other, i.e. (R1, R1), (R2, R2), (R3, R3) and (R4, R4) are outputted respectively from the preamplifiers 2 to 5. The internal output signals R1 to R4 outputted from the preamplifiers 2 to 5 are connected to one line through the respective conductive paths 6, 8, 10 and 12, and applied to one input terminal of the main amplifier 18 as the signal R. The internal output signals R1 to R4 are connected to one line through the respective conductive paths of the transistors 7, 9, 11 and 13 and applied to the other input terminal of the main amplifier 18 as the signal R. In the normal mode which is the mode other than the test mode, the signals R and Rapplied to the selecting switch 22 are amplified in the main amplifier 18 and then applied to the external output terminal 19 as an external output signal through the output transistors 25 and 26. One conductive terminal of the output transistor 25 is connected to the supply voltage Vcc through the supply terminal 24 and the other conductive terminal of the output transistor 26 is grounded. Therefore, when the signal R is at high level and the signal Ris low level, for example, the transistor 25 turns on and the transistor 26 turns off, so that the output terminal 19 becomes high level. On the other hand, in the test mode, the output signal R' of the AND gate 21 having internal output signals R1 to R4 outputted respectively from the preamplifiers 2 to 5 as the inputs is applied to one input terminal of the main amplifier 18, while the output signal R' of the AND gate 20 having internal output signals R1 to R4 as the inputs is applied to the other input terminal of the main amplifier 18. The switching between the test mode and the normal mode is carried out by the selection switch 22 in response to the control signal TM applied through the control signal input terminal 23.
The subdecode signals applied to the terminals 14, 15, 16 and 17 are applied from a nibble decoder, as shown in the articles of the prior art. The operation of the function test of the memory cell will be hereinafter described.
In testing the function of the memory cells, the logic value "0" (low level) information is written, for example, in all the memory cells constituting the memory cell array 1 by the memory testing apparatus (not shown). If each of the memory cells is functioning properly, the written information "0" will be directly read from each of the memory cells. If the output of "0" is not obtained from each of the memory cells, the memory is not functioning properly, and it is determined that the memory cell is out of order. Now, assuming that each of the memory cells functions properly, the internal output signals R1 to R4 read from the preamplifiers 2 to 5, respectively, will be "0" which is the same as the previously written logic value, while the complementary signals R1 to R4 will be "1". On this occasion, the addresses of four memory cells simultaneously read to each of the preamplifiers 2 to 5 will be designated by decoding, for example, address signals other than the most significant bit address out of the external addresses.
When the function test is carried out in the normal mode in which the information of the selected memory cells is read bit by bit to the external output terminal 19, the terminals of the selecting switch 22 are switched by the control signal TM so as to connect the signals R and Rto the main amplifier 18. On this occasion, which of the internal output signals outputted from the preamplifiers 2 to 5 should be read to the external output terminal 19 is determined dependent on which of the subdecode signals (for example, decoded signal of the most significant address of row and column) applied to the subdecode signal input terminals 14 to 17 is set at high level. For example, when a high level subdecode signal is applied only to the input terminal 14, then only the transistors 6 and 7 become conductive, the internal output signals R1 and R1 the preamplifier 2 are applied to the main amplifier 18 as the signals R and R, thereafter they are amplified therein and applied to the gates of the transistors 25 and 26. Therefore, on this occasion, (when the memory cell functions properly), the signal R is "0" while the signal Ris "1", so that the transistor 25 turns off and the transistor 26 turns on, and a signal having the logic value of "0" (low level) is read from the external output terminal 19. The remaining subdecode signals should be made high level successively in order to read the remaining internal output signals. The operation of simultaneously reading the four memory cell information and reading the stored contents of the four memory cells bit by bit successively is known as the nibble mode operation, which is provided with a normal large capacity semiconductor memory device (for example, 1M DRAM). In this manner, the logic values for function test written in the memory cells are read bit by bit to the external output terminal 19 whereby it is determined whether each of the memory cells is good or bad one by one.
On the contrary, in the test mode in which memory cells of plural bits are tested simultaneously, the nodes of the selecting switch 22 are switched by the control signal TM so as to connect the signals R' and R' to the main amplifier 18. In this case, the AND gate 21 outputs the logical product signal R' of the four internal output signals R1, R2, R3 and R4 while the AND gate 20 outputs the logical product signal R' of the four internal output signals R1, R2, R3 and R4. More specifically, the output signal R' of the AND gate 21 becomes "1" only when all of the signals R1 to R4 become "1" and, otherwise, the signal R' will be "0". In the same manner, the output signal R' of the AND gate 20 becomes "1" only when all signals R1 to R4 become "1" and otherwise it will be "0". When all of the signals R1 to R4 are "1", then the complementary internal output signals R1 to R4 become "0". Therefore, on this occasion, the signal R'="1" and R'="0". On the contrary, when all of the internal output signals R1 to R4 are "0", the complementary internal output signals R1 to R4 will be "1", so that R'="0" and R'="1". In other cases, namely, both "0" and "1" are included in the internal output signals R1 to R4, then "0" and "1" are also included in the complementary internal output signals R1 to R4 so that both signals R' and R' become "0". When R'="1" and R'="0" as described above, the transistor 25 turns on and the transistor 26 turns off through the main amplifier 18 and "1" is outputted from the external output terminal 19. In other words, when the internal output signals R1 to R4 are all "1", then the same logic value "1" will be outputted from the external output terminal 19. On the contrary, when R'="0" and R'="1", the transistor 25 turns off and the transistor 26 turns on and "0" is outputted from the external output terminal 19. Namely, when the internal output signals R1 to R4 are all "0", the same value "0" is outputted from the external output terminal 19. When R'="0" and R'="0", both transistors 25 and 26 turn off and the external output terminal 19 becomes high impedance state. Therefore, when both "0" and "1" are included in the internal output signals R1 to R4, i.e. when there exist at least one memory cell which does not function properly in the 4 bit memory cells corresponding to the internal output signals R1 to R4, then there is no output at the external output terminal 19.
As described above, by bringing the stored contents of 4 bit memory cells together as one ANDed output signal (4 bit degenerated signal) by using the AND gate, the logic value outputted from the external output terminal 19 can be assumed to be stored in all of the 4 bit memory cells. Therefore, when the logic value output thereof is equal to the logic value information previously written in the memory cells for testing the function, then it can be assumed that all of the 4 bit memory cells function properly. When no logic value information is outputted, i.e. the external output terminal 19 becomes high impedance state, it means that one or more memory cells in the 4 bit memory cells store "0" while remaining memory cells store "1", that is, at least one memory cell does not operate properly. As described above, in the test mode, the function test of 4 bit memory cells can be carried out simultaneously, so that the time required for testing the function of memory cell can be reduced to 1/4 compared with the function test in the normal mode.
Since the conventional semiconductor memory device having the test mode is structured as described above, it is effective in carrying out the function test of every single device by the memory testing apparatus. However, when the semiconductor memory device is mounted on the memory board (printed circuit board), the output terminal of the semiconductor memory device is pulled up to the supply potential through a resistance in order to stabilize the output level. Therefore, even if a malfunction is detected in the test mode and the output terminal becomes high impedance state, the level of the output terminal is pulled up to the high level and the malfunction of the memory cell can not be detected and correct decision can not be given in the function test of the semiconductor memory device. Namely, at the board level, the test mode can not be used.
A memory device in which the test mode operation is carried out by applying a voltage higher than the supply voltage Vcc to the most significant address A10 pin is disclosed in "A 60ns 4Mb DRAM in a 300 mil DIP", by T. Sumi et al, 1987 IEEE ISSCC Digest of Technical Papers, pp. 282-283. However, this memory device merely outputs the result of the function test as a trilevel decision output and is not suitable for the function test after it is mounted on the board as described above.
A memory device which outputs the result of the test mode as bilevel decision output of high and low is disclosed in "A 70ns 4Mb DRAM in a 300 mil DIP using 4-Layer Poly" by H. Mochizuki et al, 1987 IEEE International Solid-State Circuits Conference, pp. 284-285. However, this memory device has no function of outputting the result of the test mode as the trilevel decision output, so that it is not suitable for the single device test mode.
In view of the foregoing, the implementation of a memory device is strongly desired which is capable of outputting the test mode result as a trilevel decision output in the single device level and capable of outputting the result as a bilevel decision output in the board level thereby carrying out the function test of the memory cells correctly in either level.